1. Field
The present invention relates to a performance evaluation simulation performed on a software model and a hardware model for which process to be performed are provisionally determined from system specifications by using software and hardware, respectively, for performance evaluation.
2. Description of the Related Art
Conventionally, a processor, a bus, a memory, and other components for use in electronic equipment are implemented on one LSI (Large Scale Integration) and, on that LSI (system LSI), a plurality of processes are performed. Such implementation of a plurality of processes on one LSI is for the purpose of downsizing the LSI and reducing cost and consumption power, for example. However, once the hardware and architecture of the LSI is determined, an easy change is difficult, thereby increasing the difficulty in designing the functions of the LSI.
In particular, to pursue downsizing and low cost of the LSI, it is important to reduce the process load on the LSI, and each process implemented on the LSI has to be optimally divided to software (hereinafter, “SW”) or hardware (hereinafter, “HW”). Therefore, after SW or HW on which the function to be performed on the LSI is to be achieved is provisionally determined at the initial stage of LSI designing, SW/HW performance verification is performed.
In the performance verification explained above, for example, the software is written in C language, assembly language, or the like, and is executed on an actual machine model including a target processor, which is a processor implemented on the LSI for performance verification, or on an ISS (Instruction Set Simulator) for the target processor, thereby simulating the operation of the software. Also, for example, the hardware is written in RTL (Register Transfer Level) or TLM (Transaction Level Model), which are languages for describing hardware, or in a language obtained by mixing RTM and TLM, thereby simulating the operation of the hardware.
In this performance verification, when SW/HW division is performed at the initial stage of designing a system LSI, source codes of an application program and specifications of the system LSI are analyzed and divided by using man power to verify the validity of the division based on the number of cycles to be executed or the like. In recent years, various technologies for automatically performing this verification have been disclosed.
For example, Japanese Patent Application Laid-open No. 2001-142927 discloses that source codes completed to some extent are analyzed, and each processing unit is subjected to SW/HW division by taking a value of each processing unit as a determination factor, such as a throughput calculated from the number of clock cycles and an amount of consumed power calculated from the description part of a function.
Also, for example, Japanese Patent Application Laid-open No. H11-259552 discloses that architecture descriptions of a system LSI are converted to modules in units of execution to perform SW/HW division and the execution times of the respective modules obtained by executing simulations based on a benchmark program are compared, thereby determining the validity of SW/HW division.
However, in the conventional technologies explained above, it is difficult to optimally perform SW/HW division at the initial stage of designing, and it is also impossible to determine the validity of SW/HW division.
Specifically, in Japanese Patent Application Laid-open No. 2001-142927, since an analysis cannot be carried out until source codes of the application program are completed to some extent, it is difficult to optimally perform SW/HW division at the initial stage of designing. Also, in Japanese Patent Application Laid-open No. H11-259552, only the process times of the execution units are compared each other, and statistical information of a CPU (Central Processing Unit) obtained from a cache analysis of the system cannot be considered. Therefore, it is impossible to determine the validity of SW/HW division.